Instruction set
A complete reference for the Z80 and Z80N (ZX Spectrum Next) instruction set as supported by FantASM, with encodings and T-state timings. See the notation key at the end for the symbols used in the Encoding column.
Standard instructions
| Mnemonic | Encoding | T-States | Description |
|---|---|---|---|
| ADC A, r | 10001fff | 4 | Add with carry register r to Acc. |
| ADC A, n | CE nn | 7 | Add with carry immediate n to Acc. |
| ADC A, (HL) | 8E | 7 | Add with carry (HL) to Acc. |
| ADC A, (IX+d) | DD 8E dd | 19 | Add with carry (IX+d) to Acc. |
| ADC A, (IY+d) | FD 8E dd | 19 | Add with carry (IY+d) to Acc. |
| ADC HL, rr | ED 01ss1010 | 15 | Add with carry register pair rr to HL. |
| ADD A, r | 10000fff | 4 | Add register r to Acc. |
| ADD A, n | C6 nn | 7 | Add immediate n to Acc. |
| ADD A, (HL) | 86 | 7 | Add (HL) to Acc. |
| ADD A, (IX+d) | DD 86 dd | 19 | Add (IX+d) to Acc. |
| ADD A, (IY+d) | FD 86 dd | 19 | Add (IY+d) to Acc. |
| ADD HL, rr | 00ss1001 | 11 | Add register pair rr to HL. |
| ADD IX, rr | DD 00ss1001 | 15 | Add register pair rr to IX. |
| ADD IY, rr | FD 00ss1001 | 15 | Add register pair rr to IY. |
| AND r | 10100fff | 4 | Logical AND register r with Acc. |
| AND n | E6 nn | 7 | Logical AND immediate n with Acc. |
| AND (HL) | A6 | 7 | Logical AND (HL) with Acc. |
| AND (IX+d) | DD A6 dd | 19 | Logical AND (IX+d) with Acc. |
| AND (IY+d) | FD A6 dd | 19 | Logical AND (IY+d) with Acc. |
| BIT b, r | CB 01bbbfff | 8 | Test bit b of register r. |
| BIT b, (HL) | CB 01bbb110 | 12 | Test bit b of (HL). |
| BIT b, (IX+d) | DD CB dd 01bbb110 | 20 | Test bit b of (IX+d). |
| BIT b, (IY+d) | FD CB dd 01bbb110 | 20 | Test bit b of (IY+d). |
| CALL nn | CD nn nn | 17 | Unconditional call to nn. |
| CALL cc, nn | 11ccc100 nn nn | 10/17 | Conditional call to nn. |
| CCF | 3F | 4 | Complement Carry Flag. |
| CP r | 10111fff | 4 | Compare register r with Acc. |
| CP n | FE nn | 7 | Compare immediate n with Acc. |
| CP (HL) | BE | 7 | Compare (HL) with Acc. |
| CP (IX+d) | DD BE dd | 19 | Compare (IX+d) with Acc. |
| CP (IY+d) | FD BE dd | 19 | Compare (IY+d) with Acc. |
| CPD | ED A9 | 16 | Compare Acc with (HL), decrement HL and BC. |
| CPDR | ED B9 | 16/21 | CPD repeated until BC=0 or match. |
| CPI | ED A1 | 16 | Compare Acc with (HL), increment HL, decrement BC. |
| CPIR | ED B1 | 16/21 | CPI repeated until BC=0 or match. |
| CPL | 2F | 4 | Complement Acc (1’s complement). |
| DAA | 27 | 4 | Decimal Adjust Acc. |
| DEC r | 00fff101 | 4 | Decrement register r. |
| DEC rr | 00ss1011 | 6 | Decrement register pair rr. |
| DEC (HL) | 35 | 11 | Decrement (HL). |
| DEC (IX+d) | DD 35 dd | 23 | Decrement (IX+d). |
| DEC (IY+d) | FD 35 dd | 23 | Decrement (IY+d). |
| DI | F3 | 4 | Disable Interrupts. |
| DJNZ d | 10 dd | 8/13 | Decrement B, jump if not zero. |
| EI | FB | 4 | Enable Interrupts. |
| EX (SP), HL | E3 | 19 | Exchange (SP) with HL. |
| EX (SP), IX | DD E3 | 23 | Exchange (SP) with IX. |
| EX (SP), IY | FD E3 | 23 | Exchange (SP) with IY. |
| EX AF, AF’ | 08 | 4 | Exchange AF with alternate AF’. |
| EX DE, HL | EB | 4 | Exchange DE with HL. |
| EXX | D9 | 4 | Exchange BC, DE, HL with alternates. |
| HALT | 76 | 4 | Halt CPU. |
| IM 0 | ED 46 | 8 | Set interrupt mode 0. |
| IM 1 | ED 56 | 8 | Set interrupt mode 1. |
| IM 2 | ED 5E | 8 | Set interrupt mode 2. |
| IN A, (C) | ED 78 | 12 | Input from port C to Acc. |
| IN A, (n) | DB nn | 11 | Input from port n to Acc. |
| IN r, (C) | ED 01fff000 | 12 | Input from port C to register r. |
| INC r | 00fff100 | 4 | Increment register r. |
| INC rr | 00ss0011 | 6 | Increment register pair rr. |
| INC (HL) | 34 | 11 | Increment (HL). |
| INC (IX+d) | DD 34 dd | 23 | Increment (IX+d). |
| INC (IY+d) | FD 34 dd | 23 | Increment (IY+d). |
| IND | ED AA | 16 | Input from port C to (HL), decrement HL and B. |
| INDR | ED BA | 16/21 | IND repeated until B=0. |
| INI | ED A2 | 16 | Input from port C to (HL), increment HL, decrement B. |
| INIR | ED B2 | 16/21 | INI repeated until B=0. |
| JP nn | C3 nn nn | 10 | Unconditional jump to nn. |
| JP cc, nn | 11ccc010 nn nn | 10 | Conditional jump to nn. |
| JP (HL) | E9 | 4 | Jump to address in HL. |
| JP (IX) | DD E9 | 8 | Jump to address in IX. |
| JP (IY) | FD E9 | 8 | Jump to address in IY. |
| JR d | 18 dd | 12 | Unconditional relative jump. |
| JR cc, d | 001cc000 dd | 7/12 | Conditional relative jump. |
| LD r, r’ | 01fffggg | 4 | Load register r with r'. |
| LD r, n | 00fff110 nn | 7 | Load register r with immediate n. |
| LD r, (HL) | 01fff110 | 7 | Load register r with (HL). |
| LD r, (IX+d) | DD 01fff110 dd | 19 | Load register r with (IX+d). |
| LD r, (IY+d) | FD 01fff110 dd | 19 | Load register r with (IY+d). |
| LD (HL), r | 01110fff | 7 | Load (HL) with register r. |
| LD (HL), n | 36 nn | 10 | Load (HL) with immediate n. |
| LD (IX+d), r | DD 01110fff dd | 19 | Load (IX+d) with register r. |
| LD (IY+d), r | FD 01110fff dd | 19 | Load (IY+d) with register r. |
| LD (IX+d), n | DD 36 dd nn | 19 | Load (IX+d) with immediate n. |
| LD (IY+d), n | FD 36 dd nn | 19 | Load (IY+d) with immediate n. |
| LD A, (BC) | 0A | 7 | Load Acc with (BC). |
| LD A, (DE) | 1A | 7 | Load Acc with (DE). |
| LD A, (nn) | 3A nn nn | 13 | Load Acc with (nn). |
| LD (BC), A | 02 | 7 | Load (BC) with Acc. |
| LD (DE), A | 12 | 7 | Load (DE) with Acc. |
| LD (nn), A | 32 nn nn | 13 | Load (nn) with Acc. |
| LD A, I | ED 57 | 9 | Load Acc with I register. |
| LD A, R | ED 5F | 9 | Load Acc with R register. |
| LD I, A | ED 47 | 9 | Load I register with Acc. |
| LD R, A | ED 4F | 9 | Load R register with Acc. |
| LD rr, nn | 00ss0001 nn nn | 10 | Load register pair rr with nn. |
| LD IX, nn | DD 21 nn nn | 14 | Load IX with immediate nn. |
| LD IY, nn | FD 21 nn nn | 14 | Load IY with immediate nn. |
| LD HL, (nn) | 2A nn nn | 16 | Load HL with (nn). |
| LD rr, (nn) | ED 01ss1011 nn nn | 20 | Load register pair rr with (nn). |
| LD IX, (nn) | DD 2A nn nn | 20 | Load IX with (nn). |
| LD IY, (nn) | FD 2A nn nn | 20 | Load IY with (nn). |
| LD (nn), HL | 22 nn nn | 16 | Load (nn) with HL. |
| LD (nn), rr | ED 01ss0011 nn nn | 20 | Load (nn) with register pair rr. |
| LD (nn), IX | DD 22 nn nn | 20 | Load (nn) with IX. |
| LD (nn), IY | FD 22 nn nn | 20 | Load (nn) with IY. |
| LD SP, HL | F9 | 6 | Load SP with HL. |
| LD SP, IX | DD F9 | 10 | Load SP with IX. |
| LD SP, IY | FD F9 | 10 | Load SP with IY. |
| LDD | ED A8 | 16 | Load (DE) with (HL), decrement HL, DE, BC. |
| LDDR | ED B8 | 16/21 | LDD repeated until BC=0. |
| LDI | ED A0 | 16 | Load (DE) with (HL), increment HL, DE, decrement BC. |
| LDIR | ED B0 | 16/21 | LDI repeated until BC=0. |
| NEG | ED 44 | 8 | Negate Acc (2’s complement). |
| NOP | 00 | 4 | No Operation. |
| OR r | 10110fff | 4 | Logical OR register r with Acc. |
| OR n | F6 nn | 7 | Logical OR immediate n with Acc. |
| OR (HL) | B6 | 7 | Logical OR (HL) with Acc. |
| OR (IX+d) | DD B6 dd | 19 | Logical OR (IX+d) with Acc. |
| OR (IY+d) | FD B6 dd | 19 | Logical OR (IY+d) with Acc. |
| OTDR | ED BB | 16/21 | OUTD repeated until B=0. |
| OTIR | ED B3 | 16/21 | OUTI repeated until B=0. |
| OUT (n), A | D3 nn | 11 | Output Acc to port n. |
| OUT (C), r | ED 01fff001 | 12 | Output register r to port C. |
| OUT (C) | ED 71 | 12 | Output 0 to port C (Undocumented). |
| OUTD | ED AB | 16 | Output (HL) to port C, decrement HL and B. |
| OUTI | ED A3 | 16 | Output (HL) to port C, increment HL, decrement B. |
| POP rr | 11ss0001 | 10 | Pop register pair rr from stack. |
| POP IX | DD E1 | 14 | Pop IX from stack. |
| POP IY | FD E1 | 14 | Pop IY from stack. |
| PUSH rr | 11ss0101 | 11 | Push register pair rr onto stack. |
| PUSH IX | DD E5 | 15 | Push IX onto stack. |
| PUSH IY | FD E5 | 15 | Push IY onto stack. |
| RES b, r | CB 10bbbfff | 8 | Reset bit b of register r. |
| RES b, (HL) | CB 10bbb110 | 15 | Reset bit b of (HL). |
| RES b, (IX+d) | DD CB dd 10bbb110 | 23 | Reset bit b of (IX+d). |
| RES b, (IY+d) | FD CB dd 10bbb110 | 23 | Reset bit b of (IY+d). |
| RET | C9 | 10 | Unconditional return. |
| RET cc | 11ccc000 | 5/11 | Conditional return. |
| RETI | ED 4D | 14 | Return from interrupt. |
| RETN | ED 45 | 14 | Return from non-maskable interrupt. |
| RL r | CB 00010fff | 8 | Rotate register r left through carry. |
| RL (HL) | CB 16 | 15 | Rotate (HL) left through carry. |
| RL (IX+d) | DD CB dd 16 | 23 | Rotate (IX+d) left through carry. |
| RL (IY+d) | FD CB dd 16 | 23 | Rotate (IY+d) left through carry. |
| RLA | 17 | 4 | Rotate Acc left through carry. |
| RLC r | CB 00000fff | 8 | Rotate register r left circular. |
| RLC (HL) | CB 06 | 15 | Rotate (HL) left circular. |
| RLC (IX+d) | DD CB dd 06 | 23 | Rotate (IX+d) left circular. |
| RLC (IY+d) | FD CB dd 06 | 23 | Rotate (IY+d) left circular. |
| RLCA | 07 | 4 | Rotate Acc left circular. |
| RLD | ED 6F | 18 | Rotate BCD digit left and through Acc. |
| RR r | CB 00011fff | 8 | Rotate register r right through carry. |
| RR (HL) | CB 1E | 15 | Rotate (HL) right through carry. |
| RR (IX+d) | DD CB dd 1E | 23 | Rotate (IX+d) right through carry. |
| RR (IY+d) | FD CB dd 1E | 23 | Rotate (IY+d) right through carry. |
| RRA | 1F | 4 | Rotate Acc right through carry. |
| RRC r | CB 00001fff | 8 | Rotate register r right circular. |
| RRC (HL) | CB 0E | 15 | Rotate (HL) right circular. |
| RRC (IX+d) | DD CB dd 0E | 23 | Rotate (IX+d) right circular. |
| RRC (IY+d) | FD CB dd 0E | 23 | Rotate (IY+d) right circular. |
| RRCA | 0F | 4 | Rotate Acc right circular. |
| RRD | ED 67 | 18 | Rotate BCD digit right and through Acc. |
| RST p | 11ppp111 | 11 | Restart at fixed address p. |
| SBC A, r | 10011fff | 4 | Subtract with carry register r from Acc. |
| SBC A, n | DE nn | 7 | Subtract with carry immediate n from Acc. |
| SBC A, (HL) | 9E | 7 | Subtract with carry (HL) from Acc. |
| SBC A, (IX+d) | DD 9E dd | 19 | Subtract with carry (IX+d) from Acc. |
| SBC A, (IY+d) | FD 9E dd | 19 | Subtract with carry (IY+d) from Acc. |
| SBC HL, rr | ED 01ss0010 | 15 | Subtract with carry register pair rr from HL. |
| SCF | 37 | 4 | Set Carry Flag. |
| SET b, r | CB 11bbbfff | 8 | Set bit b of register r. |
| SET b, (HL) | CB 11bbb110 | 15 | Set bit b of (HL). |
| SET b, (IX+d) | DD CB dd 11bbb110 | 23 | Set bit b of (IX+d). |
| SET b, (IY+d) | FD CB dd 11bbb110 | 23 | Set bit b of (IY+d). |
| SLA r | CB 00100fff | 8 | Shift register r left arithmetic. |
| SLA (HL) | CB 26 | 15 | Shift (HL) left arithmetic. |
| SLA (IX+d) | DD CB dd 26 | 23 | Shift (IX+d) left arithmetic. |
| SLA (IY+d) | FD CB dd 26 | 23 | Shift (IY+d) left arithmetic. |
| SRA r | CB 00101fff | 8 | Shift register r right arithmetic. |
| SRA (HL) | CB 2E | 15 | Shift (HL) right arithmetic. |
| SRA (IX+d) | DD CB dd 2E | 23 | Shift (IX+d) right arithmetic. |
| SRA (IY+d) | FD CB dd 2E | 23 | Shift (IY+d) right arithmetic. |
| SRL r | CB 00111fff | 8 | Shift register r right logical. |
| SRL (HL) | CB 3E | 15 | Shift (HL) right logical. |
| SRL (IX+d) | DD CB dd 3E | 23 | Shift (IX+d) right logical. |
| SRL (IY+d) | FD CB dd 3E | 23 | Shift (IY+d) right logical. |
| SUB r | 10010fff | 4 | Subtract register r from Acc. |
| SUB n | D6 nn | 7 | Subtract immediate n from Acc. |
| SUB (HL) | 96 | 7 | Subtract (HL) from Acc. |
| SUB (IX+d) | DD 96 dd | 19 | Subtract (IX+d) from Acc. |
| SUB (IY+d) | FD 96 dd | 19 | Subtract (IY+d) from Acc. |
| XOR A | AF | 4 | Logical XOR Acc with Acc (zero Acc, clear Carry). |
| XOR r | 10101fff | 4 | Logical XOR register r with Acc. |
| XOR n | EE nn | 7 | Logical XOR immediate n with Acc. |
| XOR (HL) | AE | 7 | Logical XOR (HL) with Acc. |
| XOR (IX+d) | DD AE dd | 19 | Logical XOR (IX+d) with Acc. |
| XOR (IY+d) | FD AE dd | 19 | Logical XOR (IY+d) with Acc. |
Undocumented instructions
The index-half registers (IXH, IXL, IYH, IYL) and a handful of other opcodes are undocumented but widely supported.
| Mnemonic | Encoding | T-States | Description |
|---|---|---|---|
| XOR IXH/IXL | DD AC/AD | 8 | XOR high/low byte of IX with Acc. |
| XOR IYH/IYL | FD AC/AD | 8 | XOR high/low byte of IY with Acc. |
| OR IXH/IXL | DD B4/B5 | 8 | OR high/low byte of IX with Acc. |
| OR IYH/IYL | FD B4/B5 | 8 | OR high/low byte of IY with Acc. |
| AND IXH/IXL | DD A4/A5 | 8 | AND high/low byte of IX with Acc. |
| AND IYH/IYL | FD A4/A5 | 8 | AND high/low byte of IY with Acc. |
| CP IXH/IXL | DD BC/BD | 8 | Compare high/low byte of IX with Acc. |
| CP IYH/IYL | FD BC/BD | 8 | Compare high/low byte of IY with Acc. |
| ADD A, IXH/IXL | DD 84/85 | 8 | Add high/low byte of IX to Acc. |
| ADD A, IYH/IYL | FD 84/85 | 8 | Add high/low byte of IY to Acc. |
| ADC A, IXH/IXL | DD 8C/8D | 8 | Add with carry high/low byte of IX to Acc. |
| ADC A, IYH/IYL | FD 8C/8D | 8 | Add with carry high/low byte of IY to Acc. |
| SUB IXH/IXL | DD 94/95 | 8 | Subtract high/low byte of IX from Acc. |
| SUB IYH/IYL | FD 94/95 | 8 | Subtract high/low byte of IY from Acc. |
| SBC A, IXH/IXL | DD 9C/9D | 8 | Subtract with carry high/low byte of IX from Acc. |
| SBC A, IYH/IYL | FD 9C/9D | 8 | Subtract with carry high/low byte of IY from Acc. |
| SLL r | CB 00110fff | 8 | Shift Left Logical register r. |
| SLL (HL) | CB 36 | 15 | Shift Left Logical (HL). |
| SLL (IX+d) | DD CB dd 36 | 23 | Shift Left Logical (IX+d). |
| SLL (IY+d) | FD CB dd 36 | 23 | Shift Left Logical (IY+d). |
| INC IXH/IXL | DD 24/2C | 8 | Increment high/low byte of IX. |
| DEC IXH/IXL | DD 25/2D | 8 | Decrement high/low byte of IX. |
| INC IYH/IYL | FD 24/2C | 8 | Increment high/low byte of IY. |
| DEC IYH/IYL | FD 25/2D | 8 | Decrement high/low byte of IY. |
| LD IXH/IXL, n | DD 26/2E nn | 11 | Load high/low byte of IX with immediate n. |
| LD IYH/IYL, n | FD 26/2E nn | 11 | Load high/low byte of IY with immediate n. |
| LD r, IXH/IXL | DD 01fffggg | 8 | Load register r with IX high/low byte. |
| LD r, IYH/IYL | FD 01fffggg | 8 | Load register r with IY high/low byte. |
| OUT (C), 0 | ED 71 | 12 | Output 0 to port C. |
| IN (C) | ED 70 | 12 | Input from port C, set flags, value discarded. |
Z80N instructions (ZX Spectrum Next)
Requires Z80N to be enabled (!target zxnext or !opt z80n on). Flag notation: * affected, - unaffected, 0 reset, 1 set, ? undefined; order S Z H P/V N C.
| Mnemonic | Encoding | T-States | Flags | Description |
|---|---|---|---|---|
| ADD BC, A | ED 33 | 8 | - - - - - - | Add Acc to BC. |
| ADD DE, A | ED 32 | 8 | - - - - - - | Add Acc to DE. |
| ADD HL, A | ED 31 | 8 | - - - - - - | Add Acc to HL. |
| ADD BC, nn | ED 36 lo hi | 16 | - - - - - - | Add immediate 16-bit nn to BC. |
| ADD DE, nn | ED 35 lo hi | 16 | - - - - - - | Add immediate 16-bit nn to DE. |
| ADD HL, nn | ED 34 lo hi | 16 | - - - - - - | Add immediate 16-bit nn to HL. |
| BRLC DE, B | ED 2C | 8 | - - - - - - | Barrel roll DE left circular by B bits. |
| BSLA DE, B | ED 28 | 8 | - - - - - - | Barrel shift DE left arithmetic by B bits. |
| BSRF DE, B | ED 2B | 8 | - - - - - - | Barrel shift DE right filling 1s by B bits. |
| BSRA DE, B | ED 29 | 8 | - - - - - - | Barrel shift DE right arithmetic (signed) by B bits. |
| BSRL DE, B | ED 2A | 8 | - - - - - - | Barrel shift DE right logical by B bits. |
| LDDX | ED AC | 16 | - - - - - - | Extended LDD: if (HL) != A then (DE) := (HL); DE++, HL–, BC–. |
| LDDRX | ED BC | 21/16 | - - - - - - | LDDX repeated until BC=0. |
| LDIX | ED A4 | 16 | - - - - - - | Extended LDI: if (HL) != A then (DE) := (HL); DE++, HL++, BC–. |
| LDIRX | ED B4 | 21/16 | - - - - - - | LDIX repeated until BC=0. |
| LDPIRX | ED B7 | 21/16 | - - - - - - | Pattern fill from (HL & $FFF8 + E & 7); if != A then (DE) := t; DE++, BC–; until BC=0. |
| LDWS | ED A5 | 14 | - 0 * S S S | Layer 2 byte copy: (DE) := (HL); INC L; INC D. |
| MIRROR A | ED 24 | 8 | - - - - - - | Reverse the bits in Acc. |
| MUL D, E | ED 30 | 8 | - - - - - - | Unsigned 8×8 multiply of D and E; 16-bit result in DE. |
| NEXTREG n, n’ | ED 91 nn nn | 20 | - - - - - - | Set Next hardware register n to n'. |
| NEXTREG n, A | ED 92 nn | 17 | - - - - - - | Set Next hardware register n to Acc. |
| OUTINB | ED 90 | 16 | ? ? ? ? ? ? | OUT (BC), (HL); HL++. B is not decremented. |
| PIXELAD | ED 94 | 8 | - - - - - - | Set HL to the ULA pixel address from D (Y) and E (X). |
| PIXELDN | ED 93 | 8 | - - - - - - | Advance HL to the pixel address one line below. |
| PUSH nn | ED 8A hi lo | 23 | - - - - - - | Push 16-bit immediate nn (big-endian in stream, little-endian on stack). |
| SETAE | ED 95 | 8 | - - - - - - | Set A to the pixel bit mask $80 >> (E & 7). |
| SWAPNIB | ED 23 | 8 | - - - - - - | Swap the nibbles in Acc. |
| TEST n | ED 27 nn | 11 | S ? H P 0 0 | AND Acc with n, flags only; A unchanged. |
CSpect pseudo-instructions
Requires CSpect support (-c or !opt cspect on).
| Mnemonic | Encoding | Description |
|---|---|---|
| BREAK | FD 00 | CSpect breakpoint. |
| EXIT | DD 00 | Exit the CSpect emulator. |
Notation key
r— 8-bit register (A,B,C,D,E,H,L).rr— 16-bit register pair (BC,DE,HL,SP,IX,IY,AF).n/nn— 8-bit / 16-bit immediate value.d— 8-bit signed displacement.b— bit index (0–7).cc— condition code (Z,NZ,C,NC,PE,PO,P,M).p— restart address (00h,08h,10h,18h,20h,28h,30h,38h).(HL)/(nn)— memory at the address in HL / at immediate addressnn.
Encoding fields: fff 3-bit register (B=000, C=001, D=010, E=011, H=100, L=101, (HL)=110, A=111); ggg second register in LD r, r'; ss register pair (BC=00, DE=01, HL=10, SP/AF=11); ccc condition code; bbb bit index; dd signed displacement or immediate byte. Standard Z80 constants are little-endian; Z80N big-endian cases are noted.