Z80N Instructions

The ZX Spectrum Next adds thirty instructions to the Z80, all ED-prefixed. With the extended set turned off they decode as the two-cycle no-operation a Z80 gives an unassigned ED opcode.

The figures here are measured. The cycle counts come from a T-state-by-T-state comparison against a simulation of the FPGA design, and the flags and results from running each instruction on that simulation with seeded registers. Where published descriptions disagree, Published descriptions lists them.

Notation

Flags are SZYHXPNC: sign, zero, undocumented bit 5, half-carry, undocumented bit 3, parity or overflow, add/subtract, carry.

• –: nothing is written to the flag register.
• block: the block-transfer rule. Half-carry and add/subtract are cleared, parity is set while the counter is non-zero, the two undocumented bits are bits 3 and 1 of the accumulator plus the byte moved, and sign, zero and carry are left alone.

⚠ The block rule is not a constant byte. Its parity comes from BC and its undocumented bits from A plus the copied byte, so the value differs with the registers.

Instructions

The repeating forms take 21 T-states on every iteration that leaves BC non-zero and 16 on the last.

T-states are at the base clock, without contention. The counts most often given short elsewhere are ADD rr,nn at 16, not 14; PUSH nn at 23, not 20; JP (C) at 13, not 12; and NEXTREG rr,A at 17, not 14. On raster and copper splits a short count drifts the beam.

Examples

Notes

LDWS

ED A5 copies a byte, increments the low half of the source pointer and the high half of the destination pair, then writes the flags that second increment produces.

They are the flags of D + 1 as an addition, carry included. INC D gives the same flags in every bit but the carry, which it leaves alone.

Measured, starting from all flags set:

Adding one to 05 sets no flag, so the flag register reads 00 after it, as though it had been cleared.

Neither the counter nor the source pointer’s high half changes, so LDWS does not stop on its own when repeated.

LDPIRX

The source address is (HL AND $FFF8) OR (DE AND 7): a byte from an eight-byte pattern at HL, picked by the low three bits of the destination. HL does not advance; only DE and BC move, so the instruction fills rather than copies.

To tile an eight-byte pattern across memory, point HL at the pattern, DE at the destination and BC at the length. The pattern repeats on eight-byte boundaries of the destination, so a fill can start part way through the pattern.

The read puts the pattern address on the bus for one T-state and the destination address for the rest of the machine cycle, so anything observing the bus sees two addresses for the one read.

PUSH nn

ED 8A hh ll carries its operand high byte first. No other Z80 instruction does.

It reaches the stack in the usual order, low byte at the lower address: ED 8A 12 34 pushes $1234 and leaves $34 where the stack pointer ends up.

JP (C)

The byte read from the port does not become the address. It is shifted into bits 13 to 6 and the top two bits of PC are kept, so the jump reaches a 64-byte-aligned target inside the 16K region it is executing in.

Hardware side effects

Every instruction above finishes in the CPU’s registers and memory except three:

• NEXTREG rr,vv and NEXTREG rr,A write a Next hardware register, and nothing else. See Next Registers.
• OUTINB writes to the port in BC before advancing HL. See I/O Ports.

MUL, the barrel shifts, the pixel helpers and the block copies move data within the processor and memory only. The three above can reconfigure the machine.

Published descriptions

Each difference was found by measuring. A program written to the published description behaves differently on hardware.

1. ADD HL,A, ADD DE,A and ADD BC,A clear the carry. They are widely documented as leaving the flags alone. The design takes the carry from a bit above the truncated sum, so it is cleared whether the addition overflows or not. The three immediate forms write no flags.
2. The whole block-copy family writes flags. They are documented as leaving them alone. All six write the block-transfer rule, and LDWS writes an addition’s.
3. LDWS computes the carry. It neither keeps nor clears it.
4. All four X copies skip the write on a match, the descending pair included.
5. OUTINB leaves the flags alone. The counted port outputs take their flags from the counter’s decrement, and OUTINB has no counter.
6. PIXELAD maps a coordinate to an address, not the other way round.
7. JP (C) stays inside the current 16K, not jumping to the byte it read.
8. PIXELDN uses a specific bit repacking. The {H[4:3], L[7:5], H[2:0]} packing overlaps fields and gives the wrong address.
9. LDIRSCALE is a plain repeating copy. The opcode exists and runs, but the scaling it is named for is not in the hardware; it behaves as LDIRX.
10. NEXTREG rr,A takes 17 T-states, not the 14 some references give. The immediate form takes 20.

See also

• Machine Timing: what these cycle counts become with contention and the CPU speed.
• Next Registers: what NEXTREG writes to.

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