I/O Ports

What the Next decodes in the Z80’s I/O space, what a read returns, and what a write does. The nextreg bank reached through $243B and $253B has its own page, Next Registers.

The page describes the hardware, as the FPGA design defines it. Where a decode needs more than the port number, the condition is stated with the port. The examples are Z80 assembly.

Internal port enables

Most internal port groups are gated by a bit in nextregs $82–$85: bits 0 to 7 in $82, 8 to 15 in $83, 16 to 23 in $84, and 24 to 27 in $85. A group that is not enabled does not decode at all, so the first thing to check when a port appears dead is its enable bit. Nextregs $86–$8A are the matching enables for the expansion bus.

A reset enables every group, unless nextreg $85 bit 7 has been cleared, in which case the enables survive the reset. Bit 7 is set at power-on. Clearing bit 8 also resets the DivMMC automap, as clearing nextreg $0A bit 4 does.

With nextreg $82 bit 1 cleared, a write to $7FFD pages nothing:

        nextreg $82,%11111101   ; every group in $82 but $7FFD

ULA and Timex

The floating bus is the pixel or attribute byte the ULA is fetching from the active screen bank, 5 or 7 by the $7FFD shadow bit, while the beam is in the display area, and $FF elsewhere. It is returned under 48K and 128K machine timing only; under +3 or Pentagon timing the read returns $FF.

        ld      a,2
        out     ($FE),a         ; border red

Paging

These ports are write-only.

⚠ With $DFFD disabled, a write to it selects an AY register. The two share a decode.

$7FFD bits 0 to 2 choose the 16K bank at $C000, bit 3 the screen in bank 7, bit 4 the ROM, and bit 5 locks paging until a reset:

        ld      bc,$7FFD
        ld      a,3
        out     (c),a           ; bank 3 at $C000

Audio

A write to $FFFD is a chip select when the value ANDed with $9C equals $9C. Its low two bits then pick the chip: 11 chip 0, 10 chip 1, 01 chip 2, and 00 chip 0. Any other value selects an AY register.

Every DAC port is gated by $08 bit 3 as well as its own enable bit.

        ld      bc,$FFFD
        ld      a,$FE
        out     (c),a           ; Turbosound: chip 1
        ld      a,7
        out     (c),a           ; then its register 7

Video

        ld      bc,$123B
        ld      a,%00000010
        out     (c),a           ; Layer 2 displayed, not mapped

ULAplus is on its own page, ULAplus.

Nextreg, CTC and DMA

At 28 MHz the DMA’s memory reads take the same wait state as the CPU’s; see Machine Timing.

        ld      bc,$243B
        ld      a,$07
        out     (c),a           ; select nextreg $07
        inc     b               ; BC = $253B
        ld      a,3
        out     (c),a           ; 28 MHz

Storage and serial

MAPRAM is sticky. A write can set it and never clear it; only a hard reset or nextreg $09 bit 3 clears it.

$E7 is a small state machine. The low two bits of the value, combined with the $0A card-swap bit, select a card; the values $FB, $F7 and $7F are recognised whole, and drive both cards’ chip selects. $7F selects the flash, and only in config mode.

The Next has two UARTs, UART 0 wired to the ESP module and UART 1 to the Pi, and $153B selects which one the UART ports address. Both $153B and $163B are readable.

With the I2C data line released high, a read of $113B returns $FF.

Input

The mouse DPI setting, $0A bits[1:0], scales the motion in the mouse’s own receiver, before these counters; see Next Registers.

        ld      bc,$FBDF
        in      a,(c)           ; mouse X, counting up as it moves right

Traps, Multiface and expansion

The DivMMC automap traps at $3D00–$3DFF and $1FF8–$1FFF are taken on the instruction fetch, not through a port.

Shared addresses

Several low-byte ports collide: $1F is Kempston 1, a DAC channel and the Multiface; $3F is a DAC channel and the Multiface; $DF is the mouse, a DAC channel and, with the mouse disabled, Kempston 1. The hardware tells them apart with the internal port enables and the machine state, so a program using more than one of them sets those enables deliberately.

Unemulated hardware

• The expansion bus: nothing is attached, so the expansion-bus view is absent.
• The Pi’s I2S input, behind the $2C–$2E read path.

See also

• Next Registers: the enable bits, and the registers these ports mirror.
• Machine Timing: which of these ports are contended.

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